Control whether debugger, DMA, core 0 and core 1 can access SRAM0, and at what security/privilege levels they can do so.
Defaults to fully open access.
This register is writable only from a Secure, Privileged processor or debugger, with the exception of the NSU bit, which becomes Non-secure-Privileged-writable when the NSP bit is set.
| NSU | If 1, and NSP is also set, SRAM0 can be accessed from a Non-secure, Unprivileged context. This bit is writable from a Non-secure, Privileged context, if and only if the NSP bit is set. |
| NSP | If 1, SRAM0 can be accessed from a Non-secure, Privileged context. |
| SU | If 1, and SP is also set, SRAM0 can be accessed from a Secure, Unprivileged context. |
| SP | If 1, SRAM0 can be accessed from a Secure, Privileged context. |
| CORE0 | If 1, SRAM0 can be accessed by core 0, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. |
| CORE1 | If 1, SRAM0 can be accessed by core 1, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. |
| DMA | If 1, SRAM0 can be accessed by the DMA, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. |
| DBG | If 1, SRAM0 can be accessed by the debugger, at security/privilege levels permitted by SP/NSP/SU/NSU in this register. |